| Mosel Vitelic RAM chip marking |
| MOSEL VITELIC |
www.moselvitelic.com |
| V |
V - Mosel Vitelic
See www.moselvitelic.com/selection.pdf |
| 53 - RAM type |
53 - DRAM EDO / FastPage
54 - SDRAM
55 - SDRAM low power
58 - SDRAM DDR
62 - SRAM ultra low power |
| C - Manufacturing process |
C - CMOS |
| 3 - voltage |
5 - 5.0V
3 - 3.3V
2 - 2.5V
A - 1.8V |
| 6580 - bit organization & refresh |
1616 - 1MBit x 16 2K refresh
3332 - 1MBit x 32 2K refresh
3316 - 2MBit x 16 2K refresh
6416 - 4MBit x 16 8K refresh
6440 - 8MBit x 8 8K refresh
6480 - 16MBit x 4 8K refresh
6532 - 2MBit x 32 4K refresh
6516 - 4MBit x 16 4K refresh
6580 - 8MBit x 8 4K refresh
6540 - 16MBit x 4 4K refresh
12716 - 8MBit x 16 8K refresh
12740 - 16MBit x 8 8K refresh
12780 - 32MBit x 4 8K refresh
12832 - 4MBit x 32 4K refresh
12816 - 8MBit x 16 4K refresh
12880 - 16MBit x 8 4K refresh
12840 - 32MBit x 4 4K refresh
25616 - 16MBit x 16 8K refresh
25640 - 32MBit x 8 8K refresh
25680 - 64MBit x 4 8K refresh
25632 - 8MBit x 32 4K refresh |
| 0 - mode |
0 - FastPage
5 - EDO
G - SDRAM for graphics
[none] - Sync |
| 4 - banks |
[none] - na
2 - 2 banks
4 - 4 banks
8 - 8 banks |
| V - interface |
[none] - TTL
S - SSTL
V - LVTTL |
| T - package option |
B - BGA
C - CSP
K - SOJ
S - SOC
T - TSOP |
| C - die revision |
A/B/C ... |
| 50 - min cycle time |
60 - 60ns
50 - 50ns
8 - 8.0ns 125MHz
75 - 7.5ns 133MHz
7 - 7.0ns 143MHz
6 - 6.0ns 166MHz
55 - 5.5ns 183MHz
5 - 5.0ns 200MHz
4 - 4.0ns 250MHz
36 - 3.6ns 275MHz |
| 9914 - date of manufacture |
99 - year of manufacture
14 - week of manufacture |
| E - Temperature |
[none] 0 to 70°C
I - -40 to 85°C
E - -40 to 125°C |
| PC - RAS/CAS |
[none] CL3
PC - CL2 |
